Inductive Equivalence Checking and Relation Determinization via SAT Solving
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === The first part of this thesis focuses on verification. Retiming and resynthesis are both important techniques for sequential circuit optimization, but their applicability is limited because the verification is hard. Overcoming the verification bottleneck can enh...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91980676675822282373 |