Post-Placement Power Network Optimization for Power-Gating Design
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === Using sleep transistors to implement the power-gating design is an effective method for reducing dynamic and leakage power in advanced process. However, sleep transistors will encourage extra cost in chip area, reduce routing resource, and increase IR drop and d...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66901591310439539482 |