| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === Using sleep transistors to implement the power-gating design is an effective method for reducing dynamic and leakage power in advanced process. However, sleep transistors will encourage extra cost in chip area, reduce routing resource, and increase IR drop and design complexity. Although a denser power network can reduce IR drop, it wastes much routing area. In order to utilize this power-gating technology more efficiently, we propose a post-placement sleep transistor power network optimization method. This method can adjust the power network to meet an expected IR drop and consume smaller power network area. Two test cases are used to verify the both proposed method and design flow. Experimental results show that the proposed post-placement design flow can get accurate IR drop quickly. Furthermore, the proposed Power/Ground network adjustment methodology can also reduce 7.6% and 37.13% Power/Ground area in design 1 and design 2, respectively. So the proposed method can release more space for routing.
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