Design of High Speed Delay-Locked Loops
博士 === 國立臺灣大學 === 電子工程學研究所 === 96 === As the chip size and the clock frequency grow, the high-speed de-skew circuits and the high-speed clear clock sources are required. Due to the DLLs have the merits of the small area, no jitter accumulation and unconditional stable. So, the applications for the D...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33958572931260069152 |