Design and Implementation of High-frequency CMOS Phase-locked Loops
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === This thesis illustrates the implementation of the high frequency phase-locked loops (PLLs). In order to reduce the output jitter, several strategies are presented, which are suitable for high speed PLL design. The thesis is organized as six chapters. The first c...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/48353649274285072838 |