1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application
碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === This thesis describe a 1 voltage 0.18um CMOS 5.8GHz RF front-end for DSRC (Dedicated Short Range Communication) application. This circuit integrated a single-ended low noise amplifier (LNA), a single-ended RF input, differential IF output, Gilbert Cell types mixe...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/86647838658441816792 |