A Parallel Simulated Annealing for Floorplan in VLSI
碩士 === 國立臺北科技大學 === 電機工程系研究所 === 96 === In the VLSI physical design flow, the floorplan is a very important stage. Its result affects not only IC’s performance but also the design cost. The critical issue of floorplan is how we could minimize area and/or wire length while considering other factors w...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/kvfyy5 |