Design of the 100 MHz 10 Bit Digital Transmitter
碩士 === 國立臺北科技大學 === 電機工程系所 === 96 === This thesis presents the design and implementation of a 1.8 V, 100 MHz CMOS digital transmitter. The digital transmitter consists of a 10-bit 100 MHz digital-to-analog converter (DAC), a low-pass filter, and a fully differential current-mode line-driver, which h...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/4p324j |