Design of Low Jitter Phase-Locked Loop
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 96 === Each device has been employed in PLL would contribute the unavoidable noise to degrade the jitter performance. In addition, the power/ground and substrate noise injected to PLL which integrated in a chip also aggravates jitter heavily. This thesis proposed som...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/f28e8d |