Designing of Timing Verification Tool for FPGA Systems
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 96 === The timing specifications described by timing diagram are often used for bus transaction and sequential logic. The designer performs timing verification using simulation and emulation against the timing specification. However, these verification techniques are...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/equyc2 |