Designing of Timing Verification Tool for FPGA Systems

• Main Authors: Chiu-Chuan Yao, 姚秋全
• Other Authors: Trong-Yen Lee
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/equyc2

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 96 === The timing specifications described by timing diagram are often used for bus transaction and sequential logic. The designer performs timing verification using simulation and emulation against the timing specification. However, these verification techniques are often used for SoC/FPGA systems but with limitations. First, the simulator can only generate stimulus and then the circuit produces responses in accordance with circuit behavior. The FPGA is often used with Chipscope Pro for emulation. The Chipscope Pro, however, merely collects signal data and then displays waveforms on the screen during emulation phase. Moreover, these FPGA development tools are lack of timing verification and finding errors position in timing diagram. In this work, we propose an efficient verification method to automatically verify among golden data, simulation results and emulation data for timing verification in FPGA systems and integrate in an enhanced FPGA verification tool with graphic user interface to verify user’s design. A CPU system and an LCD IP will also be implemented for demonstrating the feasibility of the proposed tool. The experimental results show that the proposed verification method and tool rapidly find timing errors, error transactions and contents of bus when error occurs in simulation and emulation results. Therefore, the proposed tool reduces efforts and time consuming using timing diagram, and human error in debugging.