DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS
碩士 === 大同大學 === 通訊工程研究所 === 96 === Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This thesis presents a novel approach to reduce power consumption of digital multiplier based on dynamic by passing of partial products. We present three metho...
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| Format: | Others |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/68675675934914597777 |