DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS
碩士 === 大同大學 === 通訊工程研究所 === 96 === Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This thesis presents a novel approach to reduce power consumption of digital multiplier based on dynamic by passing of partial products. We present three metho...
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ndltd-TW-096TTU056500332016-05-13T04:14:59Z http://ndltd.ncl.edu.tw/handle/68675675934914597777 DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS 適用於管道式快速富利葉轉換之低功率固定長度乘法器設計 Wei-jr Wu 吳韋志 碩士 大同大學 通訊工程研究所 96 Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This thesis presents a novel approach to reduce power consumption of digital multiplier based on dynamic by passing of partial products. We present three methods for designing low power error-compensated fixed-width multipliers which keep the input and the output the same bit width. By applying the unsigned row-and-column-bypassing structure or two’s-complement row-and-column-bypassing structure or row-and-column- bypassing CSD structure, the columns and rows are passed and the switching power will be saved. The truncated part that produces the carry-out bits is replaced with several AND gates and OR gates. In other words, given two n-bit inputs, the fixed-width multipliers generate n-bit products with low product error, but use less power when compared with a standard parallel multiplier. A physical implementation of the proposed design used a standard TSMC 0.35mμ 2P4M CMOS process. Simulation results show that our two methods has 13% and 6% power reduction when supply voltage is 3.3V. We have used our methodology to design a low-power parallel multiplier for the 64-point Fast Fourier Transform processor. Simulation results show that our approach can result in significant power savings over conventional multipliers. Shuenn-Shyang Wang 汪順祥 2008 學位論文 ; thesis 77 |
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碩士 === 大同大學 === 通訊工程研究所 === 96 === Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This thesis presents a novel approach to reduce power consumption of digital multiplier based on dynamic by passing of partial products. We present three methods for designing low power error-compensated fixed-width multipliers which keep the input and the output the same bit width. By applying the unsigned row-and-column-bypassing structure or two’s-complement row-and-column-bypassing structure or row-and-column- bypassing CSD structure, the columns and rows are passed and the switching power will be saved. The truncated part that produces the carry-out bits is replaced with several AND gates and OR gates. In other words, given two n-bit inputs, the fixed-width multipliers generate n-bit products with low product error, but use less power when compared with a standard parallel multiplier. A physical implementation of the proposed design used a standard TSMC 0.35mμ 2P4M CMOS process. Simulation results show that our two methods has 13% and 6% power reduction when supply voltage is 3.3V. We have used our methodology to design a low-power parallel multiplier for the 64-point Fast Fourier Transform processor. Simulation results show that our approach can result in significant power savings over conventional multipliers.
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Shuenn-Shyang Wang |
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Shuenn-Shyang Wang Wei-jr Wu 吳韋志 |
author |
Wei-jr Wu 吳韋志 |
spellingShingle |
Wei-jr Wu 吳韋志 DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS |
author_sort |
Wei-jr Wu |
title |
DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS |
title_short |
DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS |
title_full |
DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS |
title_fullStr |
DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS |
title_full_unstemmed |
DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS |
title_sort |
design of low power fixed-width multipliers for pipelined fft processors |
publishDate |
2008 |
url |
http://ndltd.ncl.edu.tw/handle/68675675934914597777 |
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