DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS

• Main Authors: Wei-jr Wu, 吳韋志
• Other Authors: Shuenn-Shyang Wang
• Format: Others
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/68675675934914597777

碩士 === 大同大學 === 通訊工程研究所 === 96 === Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This thesis presents a novel approach to reduce power consumption of digital multiplier based on dynamic by passing of partial products. We present three methods for designing low power error-compensated fixed-width multipliers which keep the input and the output the same bit width. By applying the unsigned row-and-column-bypassing structure or two’s-complement row-and-column-bypassing structure or row-and-column- bypassing CSD structure, the columns and rows are passed and the switching power will be saved. The truncated part that produces the carry-out bits is replaced with several AND gates and OR gates. In other words, given two n-bit inputs, the fixed-width multipliers generate n-bit products with low product error, but use less power when compared with a standard parallel multiplier. A physical implementation of the proposed design used a standard TSMC 0.35mμ 2P4M CMOS process. Simulation results show that our two methods has 13% and 6% power reduction when supply voltage is 3.3V. We have used our methodology to design a low-power parallel multiplier for the 64-point Fast Fourier Transform processor. Simulation results show that our approach can result in significant power savings over conventional multipliers.