Low Cost Low-density Parity-Check Decoder Using AND Gate Based Min-Sum Algorithm

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 96 === In this thesis we proposed a new full parallel LDPC decoder, using the simple AND gates on check-node circuit operation, resulting no bit-error-rate performances lose when compare with the original min-sum algorithm. A modified min-sum algorithm is derived f...

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Bibliographic Details
Main Authors: Ching-Da Chan, 詹慶達
Other Authors: Po-Hui Yang
Format: Others
Language:zh-TW
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/pqdrua