VeriC: A Semi-Hardware Description Language to Bridge the Gap between ESL Design and RTL Models
碩士 === 國立中正大學 === 資訊工程所 === 97 === Electronic System Level (ESL) is regarded as a necessary solution to deal with the ever increasingly complex Systemon- Chip (SoC) design. Most ESL designs are modeling at the C high-level language (no matter functional C or SystemC). Although some commercial produc...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16264839033944185107 |