Physical and Electrical Properties of High-k Tb2O3,TbTixOy and YbTixOy dielectrics SONOS-type memory devices

• Main Authors: Chi Hsing Chung, 鍾濟行
• Other Authors: T. M. Pan
• Format: Others
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/02217542196353142245

碩士 === 長庚大學 === 光電工程研究所 === 97 === In the traditional floating gate memory structure, when the tunneling oxide scaled down below 10nm, the stored charge in the poly-silicon floating gate may easily leak through the defects in the tunneling oxide. In order to solve the problem of this gate structure, the SONOS structure is proposed. The conventional SONOS memory device used a silicon nitride film as the charge trapping layer. The charge stored in the silicon nitride which is discrete traps and this can improve the data retention problem of the floating gate structure. But in the traditional SONOS memory, the conduction band offset between tunneling oxide and silicon nitride is small and it will slower the program speed and worse retention property. So using high-k dielectrics to replace traditional silicon nitride has been widely studied. In this thesis, we proposed the fabrication of flash memory MIS capacitances with high-k dielectrics as trapping layer. Various different high-k material trapping layers were used in this experiment, including the Tb2O3, Tb2TiO5 and Yb2Ti2O7. We applied RTA process after deposition high-k trapping layer to increase the capability of storage charge and data retention. In the chapter 2, we used physical vapor deposition sputter method to fabricate memory capacitor with pure terbium as precursor to deposit Tb2O3 thin film. The thin film deposited on the tunneling oxide by sputter method, and followed by various temperature rapid thermal annealing to form Tb2O3 nanocrystal thin film as charge trapping layer. From the physical characteristics, the Tb2O3 thin film has actually been formed after 800oC rapid thermal annealing. The memory characteristics of the physical vapor deposition sputtered high-k nanocrystal: fast program, larger memory window have been shown from the electrical data. In Chapter 3, we introduce our experiment to fabricate Flash memory capacitor with Tb2TiO5 charge trapping layer using sputtering method. After sputtering, we use RTA treatment to form Tb2TiO5. We use X-ray photoelectron spectrometers (XPS) to investigate the chemical composition of Tb2TiO5 trapping layer and Atomic force microscopy (AFM) are done to analyze the composition of the sputtered film. The electrical characteristics C-V curve is measured to know the device performance. In Chapter 4, we introduce our experiment to fabricate Flash memory capacitor with Yb2Ti2O7 charge trapping layer using sputtering method. After sputtering, we use RTA treatment to form Yb2Ti2O7. We use X-ray photoelectron spectrometers (XPS) to investigate the chemical composition of Yb2Ti2O7 trapping layer and Atomic force microscopy (AFM) are done to analyze the composition of the sputtered film. The electrical characteristics C-V curve is measured to know the device performance.