A Multilevel K-layer Partitioning Algorithm For Three Dimensional Integrated Circuits
碩士 === 中原大學 === 資訊工程研究所 === 97 === In this paper, we propose a multilevel K-layer partitioning algorithm for 3D ICs application. The algorithm is based on the multilevel framework to coarsen the netlist successively. A K-layer partitioning procedure is applied on each level of partition during the u...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/56122728314307794751 |