Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits

博士 === 中原大學 === 電子工程研究所 === 97 === High speed and low power are two important objectives in the design of edge-triggered circuits. It is well known that the clock skew can be utilized as a manageable resource for high speed and low power. To the best of our knowledge, the circuit is never optimized...

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Main Authors:	Chun-Hua Cheng, 程駿華
Other Authors:	Shih-Hsu Huang
Format:	Others
Language:	en_US
Published:	2009
Online Access:	http://ndltd.ncl.edu.tw/handle/02553981352341947047

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spelling	ndltd-TW-097CYCU54280552015-10-13T12:04:54Z http://ndltd.ncl.edu.tw/handle/02553981352341947047 Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits 高速度低功率非零時序差異電路之資源繫結問題研究 Chun-Hua Cheng 程駿華博士中原大學電子工程研究所 97 High speed and low power are two important objectives in the design of edge-triggered circuits. It is well known that the clock skew can be utilized as a manageable resource for high speed and low power. To the best of our knowledge, the circuit is never optimized for utilizing the clock skew in the high-level synthesis stage. In this dissertation, we study resource binding of high-speed low-power nonzero clock skew circuits. First, we study the simultaneous application of clock scheduling and register binding for clock period minimization. Then, we study the simultaneous application of clock scheduling, power gating implementation selection, and resource binding for standby leakage current minimization. Finally, benchmark data consistently show that our approaches achieve very good results. Shih-Hsu Huang 黃世旭 2009 學位論文 ; thesis 85 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	博士 === 中原大學 === 電子工程研究所 === 97 === High speed and low power are two important objectives in the design of edge-triggered circuits. It is well known that the clock skew can be utilized as a manageable resource for high speed and low power. To the best of our knowledge, the circuit is never optimized for utilizing the clock skew in the high-level synthesis stage. In this dissertation, we study resource binding of high-speed low-power nonzero clock skew circuits. First, we study the simultaneous application of clock scheduling and register binding for clock period minimization. Then, we study the simultaneous application of clock scheduling, power gating implementation selection, and resource binding for standby leakage current minimization. Finally, benchmark data consistently show that our approaches achieve very good results.
author2	Shih-Hsu Huang
author_facet	Shih-Hsu Huang Chun-Hua Cheng 程駿華
author	Chun-Hua Cheng 程駿華
spellingShingle	Chun-Hua Cheng 程駿華 Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits
author_sort	Chun-Hua Cheng
title	Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits
title_short	Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits
title_full	Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits
title_fullStr	Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits
title_full_unstemmed	Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits
title_sort	resource binding of high-speed low-power nonzero clock skew circuits
publishDate	2009
url	http://ndltd.ncl.edu.tw/handle/02553981352341947047
work_keys_str_mv	AT chunhuacheng resourcebindingofhighspeedlowpowernonzeroclockskewcircuits AT chéngjùnhuá resourcebindingofhighspeedlowpowernonzeroclockskewcircuits AT chunhuacheng gāosùdùdīgōnglǜfēilíngshíxùchàyìdiànlùzhīzīyuánxìjiéwèntíyánjiū AT chéngjùnhuá gāosùdùdīgōnglǜfēilíngshíxùchàyìdiànlùzhīzīyuánxìjiéwèntíyánjiū
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Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits

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