Task Partition and Scheduling on Multiple Heterogeneous Application Specific Instruction Set Processors

碩士 === 逢甲大學 === 資訊工程所 === 97 === Stream processing applications demand high throughput. Multiple heterogeneous Application-Specific Instruction-set Processor (ASIP) architectures tend not to offer only sufficient throughput but also runtime flexibility, which cannot be provided by custom ASIC soluti...

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Bibliographic Details
Main Authors: Bo-hong Chen, 陳柏宏
Other Authors: Yi-wen Wang
Format: Others
Language:zh-TW
Published: 2009
Online Access:http://ndltd.ncl.edu.tw/handle/68773497398506205745