Trap Profile and Bias Temperature Instability of ALD-HfSiON Gate Stacks in Advanced MOSFETs

• Main Authors: Yu-Han Chen, 陳昱翰
• Other Authors: Shui-Jinn Wang
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/93690943486319773985

碩士 === 國立成功大學 === 微電子工程研究所碩博士班 === 97 === With continual downscaling, high-k dielectrics have been proposed to replace the conventional SiO2 in modern microelectronic technology. However, ionic metal oxide natures of high-k materials result in several undesired instability issues when interfacing with silicon and integrated into CMOS processes, including charge trapping near the Si/dielectric interface and stress-induced device characteristic degradation, which have become urgent issues of high-k gated MOS devices. In this work, we introduce several measurement techniques based on the principle of charge pumping and flicker noise, and carry out a comprehensive analysis of defects within the CMOS gate stack. Applying these techniques we further examine how nitridation processes of ALD-HfSiON gated MOSFETs affect dielectric quality and electronic properties. Moreover, device bias temperature instability effect also being investigated by a constant voltage stress method, and realize that nitridation processes aggravate the reliability of p-type device. We conclude that plasma nitridation brings significant improvement of dielectric film quality and device reliability. This is due to the nitridation-induced trapping centers are mostly away from channel region, which alleviates the nitridation-induced device performance degradation.