Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors
碩士 === 國立成功大學 === 微電子工程研究所碩博士班 === 97 === In this thesis, the experiment mainly studies on the hot-carrier reliability of a 0.35 μm p-type lateral double diffusion metal oxide semiconductor field-effect-transistor. Base on the degradation of every parameter, we can analyze the mechanism causing the...
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ndltd-TW-097NCKU54280452016-05-04T04:26:10Z http://ndltd.ncl.edu.tw/handle/30479749998144585484 Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors 12V高壓P型通道橫向擴散金氧半電晶體熱載子可靠度之研究 Tai-Ching Wu 吳泰慶 碩士 國立成功大學 微電子工程研究所碩博士班 97 In this thesis, the experiment mainly studies on the hot-carrier reliability of a 0.35 μm p-type lateral double diffusion metal oxide semiconductor field-effect-transistor. Base on the degradation of every parameter, we can analyze the mechanism causing the device degradation. First, the differences between HV device structure and normal LV MOS structure are introduced. The development of LDMOS device is also introduced. As process scaling down, the reliability becomes an important issue to discuss. After hot carrier stress experiment on standard dimension device, some parameters under different gate bias result in different degradation trends. TCAD simulation and charge pumping method are used to confirm the damage location induced different degradation. At last we study on lifetime issue to compare the device reliability. First we need a degradation index in lifetime model. And then we process hot carrier stress experiment on different dimension devices (S, L, and C). Then the extracted lifetime results are compared to find out which dimension variation will improve the device reliability. Jone-Fong Chen 陳志方 2009 學位論文 ; thesis 79 en_US |
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Others
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碩士 === 國立成功大學 === 微電子工程研究所碩博士班 === 97 === In this thesis, the experiment mainly studies on the hot-carrier reliability of a 0.35 μm p-type lateral double diffusion metal oxide semiconductor field-effect-transistor. Base on the degradation of every parameter, we can analyze the mechanism causing the device degradation.
First, the differences between HV device structure and normal LV MOS structure are introduced. The development of LDMOS device is also introduced. As process scaling down, the reliability becomes an important issue to discuss.
After hot carrier stress experiment on standard dimension device, some parameters under different gate bias result in different degradation trends. TCAD simulation and charge pumping method are used to confirm the damage location induced different degradation.
At last we study on lifetime issue to compare the device reliability. First we need a degradation index in lifetime model. And then we process hot carrier stress experiment on different dimension devices (S, L, and C). Then the extracted lifetime results are compared to find out which dimension variation will improve the device reliability.
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author2 |
Jone-Fong Chen |
author_facet |
Jone-Fong Chen Tai-Ching Wu 吳泰慶 |
author |
Tai-Ching Wu 吳泰慶 |
spellingShingle |
Tai-Ching Wu 吳泰慶 Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors |
author_sort |
Tai-Ching Wu |
title |
Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors |
title_short |
Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors |
title_full |
Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors |
title_fullStr |
Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors |
title_full_unstemmed |
Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors |
title_sort |
hot carrier reliability in 12v high voltage p-ldmos transistors |
publishDate |
2009 |
url |
http://ndltd.ncl.edu.tw/handle/30479749998144585484 |
work_keys_str_mv |
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