A 6-bit 220-MS/s Successive-Approximation Analog-to-Digital Converter
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === This thesis reports the implementation of a 6-bit 220-MS/s low-power high-speed successive-approximation (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is proposed to reduce the power consumption of the ADC. Compared to th...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87422351608283333666 |