| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === This thesis reports the implementation of a 6-bit 220-MS/s low-power high-speed successive-approximation (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is proposed to reduce the power consumption of the ADC. Compared to the conventional switching method, the average switching energy is reduced by 81%. This proposed ADC is fabricated in TSMC 0.18-�慆 1P5M digital CMOS process, and only occupies 0.24 mm �e 0.13 mm active area. Measurement results show that the maximum effective number of bits (ENOB) is 5.13 bits and the power consumption is 6.8 mW at the sampling frequency of 220 MHz. Also, the effective resolution bandwidth (ERBW) is 200 MHz. Accordingly, the figure-of-merit (FOM) is only 0.88 pJ/conversion-step.
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