| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === Due to the rapid growth in semiconductor manufacturing, a large number of cores can now be plugged into a single chip. However, this also results in long test time and increases the use of ATE. In this thesis, we propose a novel mixed-mode BIST architecture, called rotation-based BIST with feedback configurations, to shorten test application time. The main idea is to make use of the logic values of the internal nodes of the circuit under test (CUT) to generate some test seeds. These seeds are then rotated in the scan registers so as to generate both deterministic and pseudo-random test patterns. With this method, full fault coverage can be achieved in a short test time. Compared to traditional reseeding-based BIST, the seeds used in our scheme can be generated on-chip and do not need to be stored in ROM or be sent from exterior. We have developed a hardware determination procedure for a provided CUT to determine the high efficient BIST architecture and its test procedure to reduce test application time. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits show that the test application time to fully test any of ISCAS’85 and ISCAS’89 benchmark circuits does not exceed 2200 and 11000 test cycles, respectively.
Key words: build-in self-test, testing, test pattern generation
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