High Speed Serial Link Built-in Self Test Circuit Design
碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 97 === In this thesis, we propose a high speed serial link built-in self test circuit design for low-cost mass production. It includes a Digital Control Delay Line (DCDL) for clock delay adjustment, a Sample and Hold (S/H) module for capture the signal, a Digital-t...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/88015773626557105416 |