High Speed Serial Link Built-in Self Test Circuit Design

碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 97 === In this thesis, we propose a high speed serial link built-in self test circuit design for low-cost mass production. It includes a Digital Control Delay Line (DCDL) for clock delay adjustment, a Sample and Hold (S/H) module for capture the signal, a Digital-t...

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Main Authors:	JuMin Shih, 史汝敏
Other Authors:	ChauChin Su
Format:	Others
Language:	zh-TW
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/88015773626557105416

id	ndltd-TW-097NCTU5334007
record_format	oai_dc
spelling	ndltd-TW-097NCTU53340072015-10-13T13:11:49Z http://ndltd.ncl.edu.tw/handle/88015773626557105416 High Speed Serial Link Built-in Self Test Circuit Design 高速序列傳輸之內建自我測試電路設計 JuMin Shih 史汝敏碩士國立交通大學電機學院IC設計產業專班 97 In this thesis, we propose a high speed serial link built-in self test circuit design for low-cost mass production. It includes a Digital Control Delay Line (DCDL) for clock delay adjustment, a Sample and Hold (S/H) module for capture the signal, a Digital-to-Analog Converter (DAC) to set up the compared level. Because it does not need high-speed tester, the test can be reduced significantly. The proposal high speed serial link built-in self test circuit is designed in an UMC 90nm 1P9M Logic / Mixed Mode Low-K SP-RVT Process. The jitter resolution for the eye diagram measurement is 2.8ps. The amplitude resolution is 4.68mV, and the amplitude range is ±600mV. The chip occupies a core area of 270μm2 X 171μm2, the post-simulation eyes diagram all reaches our anticipated behavior. ChauChin Su 蘇朝琴 2008 學位論文 ; thesis 91 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 97 === In this thesis, we propose a high speed serial link built-in self test circuit design for low-cost mass production. It includes a Digital Control Delay Line (DCDL) for clock delay adjustment, a Sample and Hold (S/H) module for capture the signal, a Digital-to-Analog Converter (DAC) to set up the compared level. Because it does not need high-speed tester, the test can be reduced significantly. The proposal high speed serial link built-in self test circuit is designed in an UMC 90nm 1P9M Logic / Mixed Mode Low-K SP-RVT Process. The jitter resolution for the eye diagram measurement is 2.8ps. The amplitude resolution is 4.68mV, and the amplitude range is ±600mV. The chip occupies a core area of 270μm2 X 171μm2, the post-simulation eyes diagram all reaches our anticipated behavior.
author2	ChauChin Su
author_facet	ChauChin Su JuMin Shih 史汝敏
author	JuMin Shih 史汝敏
spellingShingle	JuMin Shih 史汝敏 High Speed Serial Link Built-in Self Test Circuit Design
author_sort	JuMin Shih
title	High Speed Serial Link Built-in Self Test Circuit Design
title_short	High Speed Serial Link Built-in Self Test Circuit Design
title_full	High Speed Serial Link Built-in Self Test Circuit Design
title_fullStr	High Speed Serial Link Built-in Self Test Circuit Design
title_full_unstemmed	High Speed Serial Link Built-in Self Test Circuit Design
title_sort	high speed serial link built-in self test circuit design
publishDate	2008
url	http://ndltd.ncl.edu.tw/handle/88015773626557105416
work_keys_str_mv	AT juminshih highspeedseriallinkbuiltinselftestcircuitdesign AT shǐrǔmǐn highspeedseriallinkbuiltinselftestcircuitdesign AT juminshih gāosùxùlièchuánshūzhīnèijiànzìwǒcèshìdiànlùshèjì AT shǐrǔmǐn gāosùxùlièchuánshūzhīnèijiànzìwǒcèshìdiànlùshèjì
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High Speed Serial Link Built-in Self Test Circuit Design

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