High Speed Serial Link Built-in Self Test Circuit Design
碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 97 === In this thesis, we propose a high speed serial link built-in self test circuit design for low-cost mass production. It includes a Digital Control Delay Line (DCDL) for clock delay adjustment, a Sample and Hold (S/H) module for capture the signal, a Digital-t...
Main Authors: | JuMin Shih, 史汝敏 |
---|---|
Other Authors: | ChauChin Su |
Format: | Others |
Language: | zh-TW |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/88015773626557105416 |
Similar Items
-
A Built-In Jitter Measurement Circuit with Auto-Calibration Techniques for High Speed Serial Link
by: Chih-ping Cheng, et al.
Published: (2013) -
Built-in Jitter Measurement Circuits Designs and Applications in Serial-Link Transceivers
by: Shu-Yu Jiang, et al.
Published: (2009) -
A Spread Spectrum Clock Generator and Built-in-Self-Test Circuit for Serial-ATA
by: MaoHsuan Chou, et al.
Published: (2006) -
Built-In Self Test Circuit Design for SDRAM
by: Hu Wen Xuan, et al.
Published: (2000) -
On-Chip High Resolution Jitter Measurement Circuit with Self-Calibration Technique for High-Speed Serial Link
by: Chih-yu Chang, et al.
Published: (2008)