Delay Optimal Compressor Tree Synthesis for LUT-Based FPGAs
碩士 === 國立交通大學 === 電子工程系所 === 97 === In this thesis, we present a compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in lookup-table (LUT) based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as ess...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22233830925515533654 |