Throughput Optimization for Latency Insensitive System with Minimal Buffer Size
碩士 === 國立交通大學 === 電子工程系所 === 97 === As manufacturing process proceeds to deep submicron (DSM) technology, global interconnect delay becomes one of the most critical obstacles in system-on-chip (SoC) design nowadays. Latency insensitive system (LIS) is a method proposed to solve variant interconnect...
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/69317888531575049740 |