A 1.25Gb/s Burst-Mode Clock and Data Recovery Circuit Using the Jitter Reduction Technique
碩士 === 國立交通大學 === 電信工程系所 === 97 === A 1.25-Gb/s CMOS half rate Burst-Mode clock and data recovery (BMCDR) circuit with a novel jitter reduction technique is presented in this thesis. There are several discrete delay time values in the programmable delay circuit (PDC) of the edge detector can be sele...
Main Authors: | , |
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Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
2009
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Online Access: | http://ndltd.ncl.edu.tw/handle/78856002001469091356 |