Design and Implementation of Duty Cycle Adjustment and Clock Synchronization Circuits
博士 === 國立中央大學 === 電機工程研究所 === 97 === With the increasing operating frequency in SoC, the clock skew would serious cause the incorrect system operation. Therefore, many synchronous circuits use to align clock skew, for example phase-locked loop (PLL), delay-locked loop (DLL), and synchronous mirror d...
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83151674204277878945 |