| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 97 === The rapid development of the process technology of chips leads to the decrease in chips size and the increase in chips density. Portable electronic devices such as laptops, mobile phones, and PDA (Personal Digit Assistant) are now lighter to carry, which meet consumers' needs and result in the growth in sales volume. The concept of System-on-Chip (SoC) proposed is therefore widely investigated. In complex very large scale integrated circuit, the pre-installed computer memory occupies a huge amount of space. It occupies 30% of space in modern microprocessor and 60% of space in System-on-Chip (SoC). Moreover, computer memory is more prone to error than logic element. These errors include hard failures and soft failures. The errors occurring in computer memory can result in incorrect data and even system crash. Consequently, it is important to protect the calculated results by improving the reliability of computer memory.
The thesis is to design a highly-reliable self-monitor/self-recovery static random access memory. We propose to design the structure of multi-column SRAM, ECC, and BICS to detect and correct the faults in SRAM and speed up the access time of the whole SRAM with BICS. Within this structure, the processing of the computer memory is under the control of BICS. If a fault is detected, the pre-installed ECC will be activated immediately for fault correction. If no fault is detected, the pre-installed ECC will be shut down to increase the access time of SRAM. The multi-column SRAM can be used to increase the reliability of computer memory as ECC can correct the faults even when SMU (Single-event Multiple Upset) occurs. In other words, this thesis seeks to develop a highly-reliable fast static random access memory which not only speeds up the SRAM with BICS but also achieve high reliability with multi-column SRAM and ECC.
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