| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 97 === In recent years, phase-locked loop is used in computers and communication systems increasingly widespread, such as clock recovery circuits and frequency synthesizer. By using digital signal to control the structure of the entire phase locked loop, the all-digital phase locked loop is developed. The all-digital phase locked loop as compared with conventional phase locked loop can be avoided in the capacitor area and the accuracy of resistance. The algorithms control the digital signal to speed up the locking of frequency and phase.
In this thesis, a multi-phase digital phase-locked loop has been designed. By using digital signal to control the entire phase locked loop, digital-controlled oscillator will output 10 phases and lock in the 55 cycles. The proposed circuit architecture with fast locking, noise suppression, jitter reduction and wide output frequency range. The phase locked loop output frequency ranges from 102MHz ~ 735MHz. The coarse state of proposed phase locked loop locks in the 19 cycles and the fine state locks in the 55 cycles.
The DVC (digital to voltage converter) has been fabricated in 0.35um and 0.18um process separately to achieve good linearity. The layout area of DVC has been substantially reduced. Additionally, the frequency of 10 phases output signal become higher through the multi-phase output. In this research, the design of PLL has a combination of differential circuit of voltage controlled oscillator to achieve the benefits of low jitter, and the advantages of all-digital phase locked loop with fast locking.
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