考慮多電壓模式設計下利用可調變延遲緩衝器以達成時鐘樹時脈偏移最小化
碩士 === 國立清華大學 === 資訊工程學系 === 97 === In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper,...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/78582227243035132271 |