針對後晶片時脈偏移最小化之有效率相差偵測器定位方法
碩士 === 國立清華大學 === 資訊工程學系 === 97 === Clock skew optimization has been an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured. There are two key...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/21599362431105470850 |