考慮變動及可靠度之大型積體電路效能及時序最佳化
博士 === 國立清華大學 === 資訊工程學系 === 97 === Under 90nm technologies, variability, such as PVT variation and multiple design modes/corners, have become one of leading causes for chip failures. The delay uncertainty raised by PVT variation may cause a design to fail its’ timing specification. In addition, it...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/73666976635157710228 |