Voltage Island-aware Floorplanning for SoC design
碩士 === 國立清華大學 === 資訊工程學系 === 97 === Reducing power consumption is an significant issue in modern System-on-Chip designs. Multiple-supply voltages (MSV's) design is one of the effective ways for dynamic power reduction, and floorplanning is the appropriate stage in the physical design cycle for...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/32082571594069564724 |
| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 97 === Reducing power consumption is an significant issue in modern System-on-Chip designs. Multiple-supply voltages (MSV's) design is one of the effective ways for dynamic power reduction, and floorplanning is the appropriate stage in the physical design cycle for applying MSV's design. Previous works have addressed the MSV's design problem at floorplanning stage by solving the voltage assignment problem and the floorplanning problem separately. In this thesis, we propose a simulated annealing (SA) based voltage island-aware floorplanning algorithm to solve the two problems simultaneously. Our algorithm is based on corner block list [1] which is efficient for integrating the evaluation process of power costs function into SA. Experimental results show that our algorithm could save 31.63\% total power consumption by forming three voltage islands in average. We could obtain better deadspace, total wirelength and power consumption than the previous work [2] as well.
|
|---|