A Low Power 10Bit 50MS/s Pipelined ADC for Image Processing Applications
碩士 === 國立清華大學 === 電子工程研究所 === 97 === A 10-bit 50-MS/s pipelined analog-to-digital converter (ADC) using an operational amplifier sharing technique in TSMC 0.35µm standard CMOS process technology is presented. A new method to suppress the effect of kickback noise in the low offset comparator is also...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/30357703958051742923 |