A Variation-Aware Current-Source-Based Model for Logic Cells
碩士 === 國立清華大學 === 電機工程學系 === 97 === In this thesis, we propose a cell delay model for accurately calculating cell delay and peak supply current in the presence of process variations. In addition to cell delay and peak supply current, the output voltage waveform for multiple-input switching (MIS) and...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99946674310006923124 |