BIST for Jitter Measurement of Charge-Pump Phase-Locked Loop
碩士 === 國立清華大學 === 電機工程學系 === 97 === This thesis proposes a BIST architecture for measuring the period jitter which is represented in two types of peak-to-peak jitter and rms jitter in Charge-Pump PLLs. Comparing with previous BIST circuit, the proposed BIST circuit changes the counter position to in...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/80781985664026760193 |