BIST for Jitter Measurement of Charge-Pump Phase-Locked Loop
碩士 === 國立清華大學 === 電機工程學系 === 97 === This thesis proposes a BIST architecture for measuring the period jitter which is represented in two types of peak-to-peak jitter and rms jitter in Charge-Pump PLLs. Comparing with previous BIST circuit, the proposed BIST circuit changes the counter position to in...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/80781985664026760193 |
| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 97 === This thesis proposes a BIST architecture for measuring the period jitter which is represented in two types of peak-to-peak jitter and rms jitter in Charge-Pump PLLs. Comparing with previous BIST circuit, the proposed BIST circuit changes the counter position to increase the measurement resolution and modifies the Charge Pump circuit of TDC to reduce the measurement error. The proposed digital control unit can decrease the testing time that also improves the leakage current effect. Thus, the measurement error is therefore reduced. The simulation results shows that the measurement resolution is about 1ps and that the measurement error is smaller than 15%.
|
|---|