A high-throughput decoder architecture for irregular LDPC codes
碩士 === 國立清華大學 === 電機工程學系 === 97 === In this thesis, we propose a high-throughput low-density parity-check (LDPC) decoder architecture, which is compatible with mobile WiMAX system. Based on vertical shuffled scheduling, we proposed a scheduling method to arrange decoding sequence. The architecture i...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83296840827573505131 |