Cache-aware task scheduling for multi-core architectures
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 97 === As the technology shrink and the increasing of the number of transistors on a single chip, multi-core processors have become major implementations to build high-performance processors. In multi-core processors, the processing cores may have separate private cach...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/78163987691432090294 |