A Multiple-Supply-Voltage Design Flow from Voltage Assignment to Floorplanning
博士 === 國立臺灣大學 === 電子工程學研究所 === 97 === As the CMOS technology enters the nanometer era, power dissipation is increasing severely and becomes a key challenge in nanometer chip design. If the increasing trend of power dissipation is still not tamed, the temperature of chips may be overheated, and furth...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/94882698579133304572 |