| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === In this thesis, an implemented fully digital calibration scheme verified in the wireless IC Testing Platform ─ HOY for the 1-bit/stage pipelined ADC is presented. The calibration design includes the Linear Histogram Testing, Missing-Decision-Level, Extracting the Number of Missing Codes, Boundary Code Modification, Overlap Cancelation, Generating the Error Coefficients, Compensation Code Output, INL/DNL Calculation. There are several novel phases in the implemented schemes, that is, the first phase is there are two levels, missing-decision-level and missing-transition-level, calibration algorithm, the second phase is collecting the total code hits to drive 1 LSB, and the third phase is on-the-fly INL/DNL calculation. The features with the above mentioned functional implementation can acquire best calibration linearity and best mismatch tolerance, degrade test time and hardware overhead, enhance noise tolerance and free strict slope constraints from the input ramp test signal circuit. The designs verified in the FPGA hardware of the DUT in the HOY platform transfer the test data to DEU by the wrapper circuit, and then pass data to ATE by the wireless RF circuit. The test program developed by Python program language in the Linux OS in the terminal can fetch the test result data, maximum INL/DNL, correctly to be shown in the screen.
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