A Variable-Interval Oversampling Clock and Data Recovery Circuit Using Interpolation
碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === A clock and data recovery circuit (CDR), which is a part of a receiver, plays an important role in a communication system. Since bandwidth of transmission channels is limited, severe jitter is produced. A CDR with higher jitter tolerance provides higher-accuracy...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53289454363866437178 |