Verification and Implementation of Bus Functional Models for USB System
碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === Due to the increasing complexity of modern SoC designs, verification has become one of the bottlenecks of the entire IC design process [5]. Current verification strategy, based on traditional hardware simulation, is not able to fulfill designer’s need efficientl...
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/77969692936967240391 |