A Time-to-Digital Converter for ADC Jitter Error Cancellation
碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === The requirement of sampling clock jitter becomes rigorous in the high-speed and high-precision analog-to-digital date conversion, usually around few pico-seconds, which is unreachable for the on-chip clock generation. A method is proposed to cancel the jitter-in...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53896464955092554696 |