Blockage-Avoiding Buffered Clock-Tree Synthesis with Clock Latency-Range Minimization
碩士 === 臺灣大學 === 電子工程學研究所 === 97 === In high-performance nanometer synchronous chip design, a buffered clock tree with high tolerance of process variations is essential. The clock latency range (CLR), which is the latency difference under different supply voltages, is defined by the 2009 ACM ISPD Clo...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14692640222663214881 |