Deadlock Checking of SystemC Designs Using Extended Petri-Net Model
碩士 === 國立臺灣大學 === 電機工程學研究所 === 97 === As SystemC is becoming the prevailing modeling language to handle the increasing complexity of the modern system-level designs, tools to conduct fast and accurate simulation and perform solid functional verification on SystemC designs have become the most critic...
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/39609164965489993043 |